Data processor with parallel operations per instruction

ABSTRACT

An electronic digital data processor particularly useful for performing tasks requiring substantial list processing computation in real (or neat real) time. The processor is organized in a manner which permits multiple operations, including arithmetic and data transfer operations, to be executed in parallel at each clock time in response to a single instruction drawn from an instruction memory. This parallel operation is achieved as a consequence of implementing the internal data registers and arithmetic circuits with multiple data inputs and by controlling them in response to a particular instruction format. Data is held constantly available at each register input bit position. The particular data input selected at any clock time for transfer into a register is determined by the particular instruction concurrently contained within an instruction buffer register. Instructions are drawn one at a time into the instruction buffer from a high speed internal instruction memory which in turn is normally loaded, one instruction block at a time, from a core memory. The instruction format includes multiple fields which separately identify operations to be executed in parallel.

United States Patent 1 Culler [451 Nov. 6, 1973 DATA PROCESSOR WITH PARALLEL OPERATIONS PER INSTRUCTION [75] Inventor: Glen J. Culler, Santa Barbara, Calif.

[73] Assignee: Culler-l'larrlson, 1nc., Goleta, Calif.

[22] Filed: Nov. 8, 1971 [21] Appl. No.: 196,310

[52] US. Cl. 340/1725 [51] Int. Cl. G061 9/16 Primary Examiner-Paul J. I-lenon Assistant ExaminerVandenburg John P. Attorney-Lindenberg, Freilich & Wasserman [57] ABSTRACT An electronic digital data processor particularly useful for performing tasks requiring substantial list processing computation in real (or neat real) time. The processor is organized in a manner which permits multiple operations, including arithmetic and data transfer operations, to be executed in parallel at each clock time in response to a single instruction drawn from an instruction memory. This parallel operation is achieved as a consequence of implementing the internal data registers and arithmetic circuits with multiple data inputs and by controlling them in response to a particular instruction format. Data is held constantly variable at each register input bit position. The particular data input selected at any clock time for transfer into a register is determined by the particular instruction concurrently contained within an instruction buffer register. Instructions are drawn one at a time into the instruction buffer from a high speed internal instruction memory which in turn is normally loaded, one instruction block at a time, from a core memory. The instruction format includes multiple fields which separately identify operations to be executed in parallel.

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SHEEI 70F 8 3E3 I @Q ii i QEQQQ bQwQQw DATA PROCESSOR WITH PARALLEL OPERATIONS PER INSTRUCTION BACKGROUND OF THE INVENTION This invention relates generally to digital data processing equipment and more particularly to an improved processor organization particularly suited to performing tasks requiring a substantial amount of computation in real or near real time on a long list of data or long signals.

An increasing number of data processing applications are arising which require that a relatively substantial amount of computation be performed in real or near real time. For example only, many scientific applications may require the execution of complex tasks involving convolution, Fouriere Analysis, spectral decomposition, special function generation (e.g. Gaussian wave functions), etc. Although the prior art is replete with various data processors, as a general rule most such processors are usually either too slow for these applications or encompass enormous amounts of hardware inordinate to the application. Some special purpose processors have been developed which are well suited to a praticular class of real time processing problems but these are generally of very limited use for other classes of problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a general purpose data processor which is capable of executing complex computational tasks very rapidly so as to be useful as a real time processor, for a variety of applications.

Briefly, a data processor is provided in accordance with the present invention, organized so as to permit a multiplicity of tasks defined by a single instruction to be initiated simultaneously and executed in parallel. More particularly, instructions are drawn, one at a time, from a very fast internal instruction memory into an instruction buffer. Each such instruction defines up to four operations including both arithmetic, logic and transfer operations, to be executed in parallel. Parallel execution of up to four operations is achieved as a consequence, in part, of implementing each of the processor data registers with four separate multi-bit data input ports. Output data from fixed sources is constantly held available at each data input port, with a particular port being selected by the instruction then contained within the instruction buffer for transferring data therethrough into the data register.

In accordance with a significant aspect of the invention, instructions are loaded into the instruction memory in blocks, as for example, from a core memory. Such a block would represent a substantial process of operations to be applied to incoming data and has the effect of specializing the processor to behave as a very fast special purpose computer. However, since the instruction memory is loaded under program control, the processor retains the characteristics of a general purpose computer, or perhaps more accurately, a selectable family of special purpose computers.

The preferred embodiment of the invention is comprised of four major units;

I. control unit,

2. arithmetic unit,

3. core memory, and

4. I/O interface.

The control unit includes elements for controlling system timing as well as for defining and controlling operations to be executed. Briefly, the control unit is organized around a high speed semiconductor instruction pad memory. Blocks of instructions are transferred from the large capacity core memory to the instruction pad memory. Instructions are read out of the instruction pad memory, one at a time, into an instruction buffer. The instruction, defining up to four operations to be executed in parallel, is decoded and control signals are then routed to the appropriate system elements, such as in the arithmetic unit. The arithmetic unit includes a semiconductor data pad memory, a plurality of registers, an adder unit, and a multiplier unit. Each register is provided with input gating which effectively enables any one of four data input ports to be selected by the control signals for inputting data to the register. Data is constantly held available at each selectable input port.

The ability to initiate and execute operations in parallel, as disclosed herein, enables highly complex computational tasks to be very rapidly performed with a minimum of hardware thereby making embodiments of the invention particularly well suited for many real time processing applications.

The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in con junction with the accompanying drawings.

FIG. 1 is a block diagram of a data processor in accordance with the present invention;

FIG. 2 is a block diagram of the control and timing unit of FIG. 1;

FIG. 3 is a block diagram of the core memory unit of FIG. 1;

FIG. 4 is a block diagram of the arithmetic unit of FIG. 1;

FIG. 5 is a block diagram of the I/O interface unit of FIG. 1;

FIG. 6 is a block diagram illustrating the portions of the control and timing unit and arithmetic unit active during the execution of a particular, but exemplary, instruction;

FIG. 7 is a block diagram illustrating the portions of the control and timing unit and arithmetic unit active during the execution of a further exemplary instruction; and

FIG. 8 is a block diagram illustrating portions of the processor active during the execution of a LOAD MACRO instruction.

DESCRIPTION OF THE PREFERRED EMBODIMENT Introduction Prior to considering the processor organization in detail, its overall functional and structural characteristics will be briefly discussed. The subject processor is an extremely fast parallel processor specifically designed to facilitate tasks such as experimental data analysis (filter, smoothing, editing, reduction) signal processing and conditioning, convolution, Fourier Analysis, spectral decomposition, control of multiple graphic display terminals, and similar tasks which require substantial computation, in real or near real time. A relatively short basic data word length of 16 bits is assumed herein. This length was selected primarily in recognior the inherently analog nature of the tasks which hereinafter, the control and timing unit 20 includes a P is intended to p high speed semiconductor instruction memory which is The subject processor is characterized by its facility loaded with a block of instructions (referred to as a to simultaneously Perform both computation and data Macro) from the core memory unit 22. Instructions are m p n and thus yield g computational Power 5 read out one at a time from an instruction pad memory and speed. Its operational characteristics are attributwithin the controlling and timing unit 20 into an inable primarily to an organization which minimizes the struction buffer also within the unit 20 and, as a consesize and complexity of the control portion while mainquence, an exacting set of control and timing signals, taining a high degree of flexibility in routing data within unique to each instruction, is generated which deterthe processor. The high degree of flexibility is intrinsic mine interconnecting paths for the data transfer within in the instruction format which permits each instrucand between the four major units and the logical and tion to specify up to four distinct operations to be initiarithmetic operations to be performed. Each instrucated and executed in parallel. This format yields a detion is then decoded within one machine cycle (I25 n gree of parallism and microprogram ability not heretosec) and may produce a plurality of simultaneous regisfore available. ter transfers and arithmetic operations. It is pointed out The subject processor is assumed to have a cycle time that although all instruction sequences are executed of 125 ns which is realized with a semiconductor nonfrom the instruction memory, certain instructions prodestructive read out instruction pad memory. An invide direct access to the core memory to thereby perstruction drawn from the instruction pad memory into mit the execution of longer instruction sequences than an instruction buffer identifies up to four operations could be executed from the instruction memory alone. which can be executed in parallel during one cycle In accordance with a preferred embodiment of the time. The allowable parallelism is achieved in part, by invention, each instruction is comprised of 28 bits providing each register with four multibit data input grouped into fields as shown below in Table I:

TABLE I T MODE J FIELD 01 0011s 1) (1 1: A

FIELD FIELD FIELD 1"11c1.| FIELD ports at which different information is held constantly The data contained within each of the fields illusavailable for entry into each bit location of a register. trated in Table I has the following meanings: The processor contains a semiconductor data pad memory, buffer registers, and special modules for per- FIELD DEFINITIONS forming the fundamental arithmetic and logical opera- T FIELD REPEAT NUMBER, this value is decre i h i pad memory ls hghtly m the mented at each clock-time (125 ns) during execution arithmetic E and selves an Fffect've buffer until it is zero. In general, the instruction is performed tween the high speed arithmetic umt and a large capacone more time than shown in the repeat numlxm lty random access core memory. As an indlcatlon of the MODE INSTRUCTON MODE, this specifies the effective Speed, a complete multiplication of 40 overall meaning of the fields OP-CODE, D-FIELD, c signed eight bit words can be accomplished in three cy- FIELD B FlELD cles or 375 ns. Furthermore, up to nine additional oper- LFIELD INSTRUCTION ADDRESS f normal ations, such as 16 bit adds, register transfers, shifts, flag cessor instruction.

checks etc can be performed in parallel during this OP C0DE=0pERATl0N TYPE after the instruction time r MODE has been selected, the set of operations that can effecuve Pam- 11"ancels ach'eved by Properly be performed in parallel is determined by the type of employing the programability of the internal instrucoperation or ORCODE tion pad memory to operate in a macro or loop mode. DCBA PARALLEL OPERATIONS each of these such a mode the mslmcuo pad memory loaded three-bit fields permit the selection of one out of eight from core memory with a block of instructions which possible operations as defined by MODE and represent a substantial process of operations to be ap- CODE.

plied to incoming data. (This data may be arriving from I From the foregoing, it will be recognized that the a penpheral device or may be drawn from a data list in data contained within each of the three bit operation core). The designated sequence of operatlons 1s exefields, A, B C and D, identifies one of eight pas cuted within the processor without requiring core ble Operations to be performed as further defincd by memory access thus making maximum use of its fast the data contained within the MODE and OP-CODE cycletime and parallel logic while eliminating the delay fields The wealth 0f operations that can be perfumed assoclated core memory accesses in parallel by the subject processor is attributable in large part to the manner in which the various registers SYSTEM ORGANIZATION 0 within the major units of FIG. 1 are implemented. All

Attention is now called to FIG. I which illustrates in of the registers will be specifically considered in conblock form the major units of a processor constructed nection with the more detailed description of each of in accordance with the present invention. Briefly, the the major units of FIG. 1. At this point, however, it processor can be considered as being comprised of a would be well to appreciate that typically, each register control and timing unit, 20, a core memory unit 22, an in the processor contains four data input ports. Data is arithmetic unit 24, and an I/O interface unit 26. The continually held available at each of the four ports and units 20, 22, 24, and 26 are illustrated in greater detail a particular port is selected for data entry by a control in FIGS. 2, 3, 4, and 5 respectively. As will be seen signal generated by the control unit 20 in response to an active instruction word drawn from an instruction pad memory in the unit into an instruction buffer also within the unit 20. More particularly, a typical register contains eighteen bit positions consisting of two flag bit positions and sixteen data bit positions. The data input path to each of the eighteen bit positions in each register is established by selected closure of the gating circuitry coupled to one of the four data input ports. For example, if the port I gating of a particular register is closed, then the data available at port 1 of all 18 bit positions of that register will be read into the register.

The output lines from any particular register are not gated but are coupled to one of the data input ports of all of the other registers to which it may be desired to transfer data from that particular register. Thus, it should be understood that no register ever really sends" data to another register. Rather data is at all times available at each of four input ports of a register and at a clock cycle time, the gating associated with a particular data input port will be closed in order to load the data available at that port into the register. Thus, in accordance with the preferred embodiment of the present invention, data can be simultaneously read into several registers in contrast to most prior art systems in which data is normally read into only one register at a time from a memory bus.

Reference will now be made to FIGS. 2, 3, 4, 5 which respectively illustrate in block form, the organization of the control and timing unit 20, the core memory unit 22, the arithmetic unit 24, and the I/O interface unit 26. The elements and internal organization of each of these major units will be considered individually but no attempt will be made to exhaustively disclose the hardware details since such information is well known in the art and not particularly germane to the teachings of the present invention. The organization and functioning of each of the major units will be discussed primarily as they relate to an understanding of the parallel operations tables to be discussed hereinafter. It is pointed out that the unusual effectiveness of the disclosed processor is primarily attributable to the instruction format and operation sets illustrated in tabular form in the parallel operations tables.

CONTROL AND TIMING UNIT 20 Initially considering the control and timing unit 20, it is pointed out that this unit is organized around a high speed 64 word X 28 bit semiconductor instruction memory. The instruction pad memory is utilized to store blocks of instructions which are loaded into the instruction pad memory by a set of input lines 42. More particularly, blocks of instructions, i.e. Macros, loaded into the control pad 40 are nonnally drawn from the large capacity core memory unit 22 through registers 11 and ll of the arithmetic unit 24 to be discussed hereinafter. As will be seen hereinafter, instructions executed from the instruction pad memory can provide access to the large core memory 22 to thereby enable long and complex sequences to be executed while still permitting very rapid processing of instruction sequences which can be fully contained within the instruction memory. In response to certain instructions (i.e. link jump) the instruction pad 40 can be loaded via multiplexer 43 which functions to derive some bits from register 12 and others from the instruction buffer 44. Instructions are read out, one at a time, from the instruction pad 40 on output lines 46 from locations defined by the contents of an instruction pad address register 48. As will be recalled from Table I, each instruction is comprised of 28 bits grouped into eight fields. The .l field information which identifies the address of the next instruction to be read from the instruction pad is normally routed from the output lines 46 to the instruction pad address register 48. The OP CODE, D, C, B, and A field information is normally routed to in struction buffer 44 where it is held during the instruction execution time. The two bit mode field is routed to a pair of mode flip-flops 50. The instruction buffer contents is decoded by decoding circuitry 54 which in turn develops control signals which are routed to the appropriate elements of the major processor units. Although instructions are normally loaded into the instruction buffer 44 from the instruction pad 40, single instructions can also be loaded into the instruction buffer 44 from the core memory via a path which en compasses register I] in the arithmetic unit 24.

In addition to developing control signals, the unit 20 of FIG. 2 develops timing pulses in response to 8 MHz clock pulses provided by clock generator 56, defining a n sec. cycle time. A four bit timing counter 58 and an eight bit word counter 60 are provided for developing timing signals for instructions which require execution times in excess of one cycle time, i.e. 125 ns.

More particularly, the four bit timing counter 58 is loaded with the T field information of an instruction read from the instruction pad which indicates how many times the instruction is to be executed. In the exe cution of most instructions, when the next instruction is accessed from the instruction pad and the .l field thereof is loaded into the instruction pad address register 48, the T field thereof is concurrently loaded into the timing counter 58. It is thereafter decremented at each clock time until it reaches zero. This permits the instruction execution time to be extended to enable an instruction to be executed over more than one cycle and also enables the same instruction to be executed a multiple number of times. In the execution of certain instructions e.g. an instruction (OP CODE 14) to load the instruction pad from core memory, the timing counter 58 is not decremented at the first clock time after being loaded but its contents is stored in a timing counter buffer register 59. At the same time, the number of words (as specified by A and B fields) to be loaded into the instruction pad is entered into a word counter 60. The timing counter is thereafter decremented at each clock time. When the timing counter reaches zero, if the word counter has not yet reached zero, the original value in the timing counter 58 is reloaded therein from the timing counter buffer register 59 and the word counter is decremented. The process of counting down the timing counter 58 continues until the word counter reaches zero at which time a new instruction is loaded into the instruction buffer 44 and a new T field is loaded into the timing counter 58.

As has just been mentioned, the function of the word counter 60 is to count the number of words to be loaded into the instruction pad when executing a load instruction (i.e. OP CODE 14) which will be discussed in greater detail hereinafter.

As a basis for understanding the parallel operations tables to be discussed hereinafter, the following control unit 20 registers and line sets listed by name and typical usage, are of particular importance:

TABLE II Name Bits Usage Control Unit 20 E, 8 Extention of E IE. 4 Extension of E. E,

IR 28 Instruction Pad 40 Output Lines IB [6 Instruction Buffer 44 IA 6 Instruction Pad Address Register 48 TC 4 Timing Counter 58 IM 2 Mode flip-flops 50 CORE MEMORY UNIT 22 Attention is now called to FIG. 3 which illustrates the core memory unit 22 in greater detail than is shown in FIG. 1. The core memory unit consists ofa 16 bit memory address register 70 and four self-contained 4K X 18 bit core modules 71a, 71b, 71c, 71d. The core address register 70 is loaded from the adder sum output lines (ADS) from the arithmetic unit 24 or from the instruction buffer (IE) 44 of the control and timing unit 20. Each core module includes a core data register 72. The output lines (CD) from all the registers 72 are coupled to an ll register and data pad input bus in the arithmetic unit 24 to be discussed hereinafter. The input lines to the registers 72 are derived from the arithmetic unit register II for transferring data into the memory. The

word location in each module for reading and writing is defined by address information entering into buffer address registers 74 from the output lines (CAR) of the core address register 70.

In the operation of the core memory unit, a fourteen bit address entered into the address register 70 is required to select a unique word in the 16K word core. Bits l4 and are decoded to generate a module select signal which functions to select one of the four core modules. The module select signals is gated with a timing signal (not shown), generated within the control and timing unit 20, to derive a core initiate signal which initiates the following actions:

1. starts the timing chain within the selected core module; and

2. causes bits 0 through 13 of the core address register 70 to be transferred to the address buffer register 74 of the selected module. The module select signal is used within the selected module to derive a control term which gates the contents of the internal core data register 72 onto the core output data lines (CD).

The core unit registers and lines significant to an understanding of the operations tables set forth hereinafter are as follows:

TABLE III Core Unit Name Bits Usage 22 CAR 16 Core Address Register CD 18 Core Data Register Read Out ARITHM ETIC UNIT 24 Attention is now called to FIG. 4 which illustrates the principal elements of the arithmetic unit 24. The arithmetic unit is comprised of a semiconductor memory or data pad 90 comprised of 64X l6 bit locations. Information is read out of the pad 90 onto output lines (PD) from locations defined by the content of a pad address register 94. Information is written into the pad 90 through input lines 96 via a pad input bus 98. In addition to the pad address register 94, the arithmetic unit includes six other principal registers respectively identified as A1,", A2, [2, M1, M2. Each of these six registers has four selectable data input ports as has been previously mentioned. Information is constantly held available at each of the data input ports and a selected port is closed in response to control signals (not represented in FIG. 4) developed by the instruction decoding circuitry 54 of the control and timing unit 20.

The arithmetic unit 24 further includes a sixteen bit adder circuit 99 and an eight bit multiplier circuit 100. The register M1 and M2 respectively hold the eight bit multiplier and multiplicand when multiplying eight bit numbers. Longer numbers can be multiplied by distributive algorithms, as is known in the art. The multiplier and multiplicand are stored in registers M1 and M2 in sign magnitude form. Typically, numbers are represented in the system in twos complement form. The adder module accepts input directly from six registers and is capable of forming the: sum, difference, increment, decrement, and, or, exclusive or, and two's complement of l6-bit numbers. The adder output ADS or adder complement ADS* may be gated to several registers. A complete add operation requires one cycle-time of n sec, however, as many as three other operations may be occurring in parallel. Carry and overflow detection are automatic following each adder operation.

The following registers and lines of the arithmetic unit are significant to an understanding of the parallel operations tables to be discussed hereinafter.

TABLE [V General Function Name Bits Usage Arithmetic Unit 24 A 16 Coupled to PAD A, l6 Coupled to multiply operation and core address register I, I8 Coupled to core l 16 Coupled to multiply operation and core address register M 8 Multiply first register M, 8 Multiply, second register FL 8 Flag register left,

collection of all left flags FR 8 Flag register right,

collection of all right flags PA 6 Pad Address Register OF/CF 2 Overflow and carry flags (to AD) ADS l6 Adder output ADS l6 Adder complement output PDl l6 Data Pad Input MPP l6 Multiply Output MS I Multiply Output Sign All of the registers and lines indicated in the foregoing list have been previously mentioned except for flag registers FL and FR and overflow and carry flipflops OF and CF.

Flag register FL consists of eight bit stages, each as sociated with a different one of registers S, D, M 1, M2, [1, [2, A1, A2. Similarly, flag register FR consists of eight bit stages, each associated with one of the registers S, D, M1, M2, [1, I2, A1, A2. The flag registers are used primarily to store sign hits, as will be seen hereinafter, each of the flag register bits can be individually examined in response to a bit test" instruction (OP CODE 15) to determine whether ajump address operation should be executed.

l/O INTERFACE UNIT 26 Attention is now called to FIG. 5 which illustrates the organization of an exemplary l/O interface unit 26. It will be appreciated that the particular mix of peripheral devices employed is not at all critical to the present invention but is illustrated only as constituting a repretypical embodiment of the invention will be set forth. For convenience, the instructions are first grouped according to MODE; second (within a MODE) according to OP CODE; third (within an OP CODE) according to sentative example. For present purposes, it is only nec- DCBA field definition; and last, the particular transforeSSary to Consider thos elemen s Within the 1/0 intermation resulting from a given numerical value within a face unit which interface directly with the major profield. For the sake of easy reference, these groupings cessor units previously mentioned. Thus, for example, are presented in tabular form. p ti a anehtiofl is callffd t0 the D and S g Table VI, set forth hereinafter, identifies the meaning ters. All input/output functions take place only on com- IQ f h io fi ld f n instruction word of MODE a from the PTOCeSSOY- Thus, instructions and P 0. ln interpreting Table V], the significance of each D, ripheral device addresses are transferred from the in- C, B, d A field for a particular OP CODE can be destruelion buffer 44 0f th C MIC ni 0 t D g termined. For example only, if a particular instruction ter of the 1/0 interface unit 26. The instruction is then d d fi i MODE 0 lso defines an OP CODE 1, decoded by decoder 101 and routed to the appropriate l5 h n th me in of the D, C, B, and A fields are deperipheral device determined by decoder 102 decoded termined by sighting to the right across the table from the device address. Output data is transferred on com- OP CODE 1. As can be seen, the value represented by mand from the Arithmetic unit registers eg 12, A2, to the three bit D field will define a particular operation the appropriate l/O device e.g. a digital to analog conidentified in the ADDER OPERATIONS Table XV. verter 104 for use, for example, with a display storage 20 The three bit C field value will identify the source of tube. An input/output device can signal the processor data to be transferred into the E register. The value of by turning on a unique interrupt bit in the S register. the three bit 8 field will identify the source of data to Upon recognition of this interrupt, the processor can be transferred into the pad address register (PA) and command the particular input/output device to output similarly the value of the three bit A field will identify ts Status 10 the /0 bus from which i a be loaded t the source of data to be transferred into the l2 register.

TABLE v1 Mode l) 01* Code 1) Field (1 mm C Y A 1 11 -11 1 i Instructions format tulllv r r r r 0 Special Parallel Instructions 1 Addrr Row E1, E2 PA 1: 2 (1 Field =11 El, E2 A2 Pl) 3 in Adrlrr M1 M2 Al 4 Operations M] M3 12 5 T111111) 1], E2 ll 1'!) 6 PA 1 1) 7 PA A1 10 A2 A1 11 Arlrlvr Row Adder (olumn ll Al 12 A: 1: 13 11 1e 14 Load typo Words 15 Bit test .lump zulilrvss lu' Logii' typo Sprrillvr or jump :ulrlrwss 17 Return address Nul. usml the El register. Data from an [/0 device can also be As an example of the variety of instructions possible, loaded into register E1 in a similar fashion. The El mg the functional operations which may be carried out in ister is rather tightly coupled to the arithmetic unit so MODE 0 are described below: that its content can be easily transferred to the Register sop CODE 0: SPECIAL PARALLEL OPERATIONS Allows loading of up to six selected registers in paral- The registers and lines of the 1/0 interface unit which 1 Th ist s are A], A2, 1], l2, M1 and M2. are particularly significant to an understanding of the *OP CODES NORMAL ADD parallel operations tables to be discussed hereinafter Allows the execimon of one of Seven addelufunctions m as in parallel with the loading of three other REGISTERS.

TABLE V The registers are selected by the OP CODE used.

Gem *OP CODES 6-13: FlXED-DESTlNATlON ADDS era] Regi ter N of Allows the execution of 63 different arithmetic and F32 logic functions, including: add, subtract, negate, sign lnpml TR [6 Real Time Counter magnitude and twos complement conversion, incre- Output (1,, sec increments) ment, decrement, AND, OR, exclusive OR, tests for U 126 El 16 Coupled to Enema] U0 equality, greater or less than, and many others. Two units and pads I other register-functions may be performed in parallel. D 8 gegtlgfarcommumcauons *0? CODE 14: [:OAD I I S 8 Interrupt Status Register Allows the loading of all or part of 1nstruct1on-pad or D] 16 Device input li data-pad. The instruction-pad can be loaded from the core-memor or from the dataad. The dataad can PARALLEL OPERATIONS TABLES 65 y p p The instruction format will be recalled from Table I. Hereinafter, the variety of operations and combination of operations available within the instruction set of a be loaded from core-memory. The instruction also allows for storing all or part of data-pad into the corememory. Several additional special load operations are possible.

OP CODE 15: REGISTER TESTS Allows for testing of a specific bit in several registers. OP CODE 16: CONDITION TESTS Allows for several different types of operations including testing for pad addresses, the comparing of bits in several registers, the setting and clearing of bits in some registers, etc.

*OP CODE 17: LINK-JUMP Allows jumping to other programs in instruction-pad and returning to a selected place in instruction-pad. The meanings of these OP-CODE groups then change for MODES, I, 2 or 3. Furthermore, the specific events 'IAIIL E VIII OI CODE asauusu s-Per? ADDER ROW E MODE .2

l) FIELD C FIELD B FIELD A FIELD (C FIELD= in AD DER OPERATIONS TABLE) RETURN AI) D HESS JUMI' ADDRESS JUMI ADDRESS SET I'A T M] OP D CBA 0054 63 T 0, only one clock-time of I- nsec will be needed.

M 0, mode zero (see summary above).

I 5, next instruction will be found in instruction address 5.

OP =4, determines a class of add and transfer possibilities.

D 6, permits the contents of registers A, and I, to

enter the adder and gates the sum back to I,.

C 3, enables bits 0-7 of I, to go to M, (one side of the multiplier) and the l, flag right is transferred to the M, flag right.

B 4, enables bits 0-7 of A, to M, (a multiply inputregister) and the A, flag right to the M, fiag right.

A 4, enables the current multiply product to I,

(without the sign bit).

As a net result, the following functions all would take place in the single clock-time of l25-nsec.

l. A, I, I,

M1; I l MIFI) It will be recalled that Table VI related to instructions defining MODE 0. Instructions defining MODE 1 instead of MODE 0 cause the same operation as was indicated in Table VI except for the following modifications indicated in Table VII:

TABLE VI] Mode 1 OP CODES l, 2, l3 transfer the ADDER output to CA.

In the MODE 2 instructions indicated in Table VII], the D and C fields generally specify the inputs to the adder, and the OP CODE specifies the destination of the adder output. The B and A fields respectively contain the address to be entered into the pad address register 94. OP CODES 0, 5, 14, 17 have no MODE 2. OP CODE 15 is a scan test of the register specified by the two most significant bits of the D field. OP CODE 16 (DC is a scan test of the S register. This scan test allows sequential testing of all bits in a register and exits upon finding a one bit. OP CODE 17 is the same as MODE 0 except, in addition, PA is set.

Table IX indicates the utility of MODE 3 instructions:

TABLE IX Mode 3 OP Code D Field (3 Field B Field A Finld New Value of ()A TABLE Xa.-IIIC. TABLES OF FIELD DEFINI'IIONS BY OP-UODE NUMBER OI code 11 Table, MOdi'S (1,1

TABLE Xa.lIIC. Continued TABLES OF FIELD DEFINITIONS BY OP-(TODE NUMBER OP code Table, Modes 0,1

It will be noted that Tables Xa and Xb relate to OP CODE 0 for MODE 0. From Table VI, it will be recalled that in MODE 0, OP CODE 0 causes special parallel instructions to be executed as defined in detail by Tables X0 and Xb. The individual bits of each of the D, C, B and A fields identify operations to be executed. More particularly, it will be recalled that the A field is comprised of bits 0, l and 2. These three bits can define TABLE XI.OP CODES 1-13 a binary value anywhere between 0 and 7. For each of these binary values indicated in the lefthand column of Table Xa, the three bit A field will cause the operations indicated in the A field column to be executed. Thus for example, if bit 0 in the A field is a I then a 0 will be loaded into the A] register as indicated by Table Xb. Bit 2 of the A field is a l and bits I and 0 are both 0, and will of course mean the A field has a binary value of 4. Sighting to the right along row 4 of Table Xa, it will be noted that the operation called for is to transfer the contents of the pad output lines into register II. This operation is also represented in Table Xb wherein it will be noted that a l in bit position 2 of the A field causes this operation. By way of further explanation, if all three bits of the A field are I then the three operations indicated in Table Xb will occur and this is verified by sighting to the right along row 7 of Table 10a under the A field column.

Attention is now called to Tables XI, XII and XIII set forth hereinafter which respectively identify the operations to be executed in response to the various possible values of the A, B and C fields for OP CODES 1-13, MODES 0 and l.

The interpretation of Tables XI, XII, and XIII should be readily apparent. By way of example, consider an exemplary instruction, e. g., MODE 0, OP CODE 1 with an A field value equal to 3. From Table VI it will be recalled that for OP CODE 1, the value of the three bit A field identifies a source of data to be transferred into the register 12. This is in agreement with Table XI which in the middle row indicates that for OP CODE I, register I2 is the usual destination register. If the three bit A field, for example, defines a binary value of 3, then the contents of the ll register is to be transferred into the 12 register. As a further example, if the three bit A field defined a binary value of 4, then the output of the multiplier would be transferred into the I2 register. Most of the other entries in Tables XI, XII and XIII can be similarly interpreted. Those entries depicted with a double box signify operations which do not transfer data into the usual destination register.

Table XIV set forth hereinafter identifies the significance of the three bit C field for OP CODES 1-4,

MODE 2.

REGISTER OPERATIONS TABLE-MOI)ES (I, l

TABLE XIV.-( P CODES 1-4 REGISTER OPERATIONS TABLE-MODE 2 T FIELD must be 0101- these instructions. T FIELD must be 1.

Attention is now called to Table XV set forth hereinthat the ADDER OPERATIONS table is referenced in after which constitutes a fixed destination ADDER OP- executing instructions having OP CODES 1-13, ERA'IIONS table. From Table VI, it will be recalled MODES 0, 1 and 2.

TABLE XV.ADDER OPERATIONS TABLE I FIXED DESTINATION OP CODES 113 MODES 0,1,2

()1' (101) ES 1-5, this column only.

NOTE:

1. 164111, SIGNED MAGNIIUDE form is converted to 16-bit 2s COMPLEMENT.

2. 111-1111. 2's COMPLEMENT (arm is converted to 16-bit SIGNED MAGNITUDE 16-bit SIGNED MAUNIIUUF,

1orn1is AKFI AK [1 16bit magnitude 16-bit twos complement number, with 111((17) =slgn 3. Al+A'll-Cl"- Al, (IARIIY CF. The Carry Flag and tho Overflow Flair. are sot Ivy any ndtl operation which has a destination.

0 1[J+1 IA, (111250 nsoc to execution tiineA=AND; V=OR; V=oxclusive OR.

In order to interpret Table XV, consider, for example, an instruction having an OP CODE 7, MODE 0. Moreover, assume a D field value of 4 and a C field value of 3. These C and D field values will reference us and a C field equal to 2. Initially referencing Table XV, it can be noted that this D and C field configuration causes the content of the Al register to appear at the output AD of the adder and then to be transferred into to an entry in Table XV which indicates that the con- 5 the register A2. If as part of this same instruction, the tents of the Al register is incremented by l and then A field defined a value of 2 for example, then by referre-entered into the Al register. It will be noted that all encing Table XI, it will be recognized that the adder of the entries in Table XV specify both an operation, output (in this case Al) instead of being transferred which determines the adder output AD, and a destinainto register A2, will be transferred into register [2. tion for the adder output. Attention is now called to As a further example again assume OP CODE 12 Table XV] which constitutes a selected destination and D and C fields respectively having values 6 and 4 addc.r operanons table.whl.ch enables the mstmcuon to Referencing Table XV, it will be noted that the sum of a selected destmanon or.the adder i the contents of registers 11 and 12 will appear at the n be noted the .enmes m Tab]? ldem'fy output AD of the adder. This output will normally be operatlons to be execmed P to k C an 15 directed to destination register II as represented in D f The ldpmlfied m Table Y Table XV. However, if the A field has a value of 2, then are ldemlcal to these Identified m The the adder output (in this case the sum of register I] and ference between Tables XV and XVI is that Table XV 12) will be directed into register [2. identifies destinations for the adder output as well as the operation to be performed by the adder, Table XVI It will be recalled from Table VI that OP CODE 14 does not identify the destination for the adder output n ifi a load yp instruction Generally. load yp b t elies u on the A and B fields to identif a ele ted instructions are utilized for transferring one or more destination. When a selected destination is identified, Words between components of the processor such as it aborts the path to the normal destination register between the core memory, instruction pad, data pad, specified by Table XV. peripheral devices, etc. The detailed operations exe- More particularly, as an example, consider an instruction having an OP CODE 12, a D field equal to 4,

cuted in response to each load type instruction are defined in detail by Table XVII.

TABLE X\'I.ADI)ER OPERATIONS TABLE II, SELECTED DESTINATION 0P CODES 1-13, MODES 0,1,2

LOAD PI) MACRO WAIT TIALF EXECUTE FULL EXECUTE MODE I is the samv as nlmvn except for tlw following:

ENABLE I/l) Notes: The last instruction is moved to Ill and is executed.

1 words 1must=0.

It will be recalled from Table VI that OP CODE 15, MODE and l, instructions define bit tests. Table XVIII set forth hereinafter indicates the particular bit test defined by an OP CODE 15, MODES 0, l instruction for different configuration D and C fields. That is,

the value of the D and C fields identifies a particular bit to be tested. If that tested bit matches the MODE, i.e. the condition is met, then the jump address specified by the A and B fields of that instruction is loaded into the 6 ElR a s 7 ElL 7 1 Attention is now called to Table XIX which illustrates the operation to be performed in response to an OP CODE 15, MODE 2 instruction. This instruction allows the testing of each bit of four different registers, i.e. flag (F), A2, 11, E1, in sequence, for a I bit. The D field of a scan test (i.e. OP CODE 15, MODE 2) instruction identifies the desired one of the four registers. In scanning, when a 1 bit is encountered, the pad address is decremented and the next instruction is loaded from the instruction pad location given by the jump address. If, in scanning, no 1 bit is encountered, the pad address is decremented and the instruction address by the .I field is next accessed. It will be recalled from Table VI that OP CODE 16, MODE 0, l instructions normally identify conditional tests and in the event the test is met, then the jump address designated by the A and B fields is used to access the next instruction. Thus, OP CODE 16 is similar to OP CODE 15 except that OP CODE 16 enables several different tests to be defined as represented in Tables XX and XXI.

TABLE XIX.-OP CODE 15, MODE J 1) Field Specifies Register REGISTER ASSIGNMENT OF FLAGS S YNC 1 ior i-xuctly (Jtll clock at a time interval determined by the contents of TI. (S00 Section V U, Timer Instructions).

Norms:

If llA-+IA, add nscc to execution time. If J+I-IA, add 125i! nsl-c to uxvcution time.

Instructions whosu results are not designated are undefined; tlll'll' results are indeterminate. MODE 1: In general, Under MODE 1 tests for equality become tests (or inequality, and instructions which set It hit=l), set it 1.

*SYNC=1 for exactly one clock at a time interval determined by the contents of 'I[. (See Section V G, Timer Instructions).

Norss:

II BA IA, add 125 nsec to execution time. If J+1 IA. add 250 nsec to execution time.

UP CODE 16 TABLES, MODES ANDI instructions whose results are not designated are undefined 1) Field C Field SHIFT B Field A Field 0 N0 OP 0 NO OP 1 LSAI, Fill w/zero 1 LSII, Fill w/zcro .l LSAI, Fill w/Aln Al 2 LSll, Fill w/Ilu I1 3 LSAI, Fill W/lln 3 LSll, Fill w/Al 4 RSAZ, Fill w/zcro 4 RS125, Fill W/zcro 5 RSA2, Fill W/AZn 5 R812, Fill w/[Zu t) RSAZ, Fill w/AZ A2 (I R812, Fill w/Ill I2 7 RSAZ, Fill w/I2q 7 RSIZ, Fill w/AZu LS=lcIt shift RS=rightsl1iIt 1) Field C Field TRANSFER I1 FLAGS 13 Field A Field 1) NO OP 0 NO OP OP CODE 16 TABLES, MODES 0 and l D Field C Field Ill. 5 0 I MEMORY CONTROLS A Field 0 Clear WRT, BUF, RMW 1 SET WRT (write mode) 2 SET BUF (buflcr or split mode) 3 SET RMW (rcad-modify-write mode) WRT write mode. At the next core initiate, the contents of ll will be written into the core ccll addressed and WRT will be cleared. (ll must remain unchanged for three clock times after the core initiate.)

lccted cell are read as in the normal Read-Restore cycle. It is, however, possible to alter the data in I] and to store the altered data into the selcctcd cell by executing a CA+0* CA instruction. RMW mode is cleared at the end of the read-modify-write cycle. The minimum cycle time for thisopcration is L uscc, or 9 clocks.

As an example of how to interpret Tables XX and XXI, consider an OP CODE 16, MODE 0 instruction. This refers to Table XX and as an example, if a C field equal to 2 and a D field equal to l are defined by the instruction, then the test is to determine if the contents of the pad address register is equal to 0. If the condition is met, then the jump address contained in the A and B fields is transferred to the instruction address register. It is also pointed out that OP CODE 16 is utilized to cause certain actions such as shift (DC 40), transfer flags (DC 43), core control (DC 50), transfer into pad (DC 63), and shift flags (DC 41).

Table XXII illustrates the test conditions for a scan test instruction OP CODE 16, MODE 2. This instruction is a scan for 1 test operating on the S register. The pad address contains the number of the bit to be tested. 

1. A data processing system including: instruction pad memory comprised of a plurality of locations, each capable of storing a multibit instruction word; an instruction address register means for uniquely identifying one of said instruction pad locations to produce a representation of the instruction word stored therein on output lines of said instruction pad, each of said instruction word representations including representations of a multibit ADDRESS field, a multibit OP CODE field and two or more multibit OPERATION fields; a multistage instruction buffer; means for storing said representations of said OP CODE and OPERATION fields in said instruction buffer; a plurality of sets of OPERATION decoder circuits, each circuit in a set being responsive to a different OPERATION field stored in said instruction buffer; OP CODE decoder means responsive to said OP CODE field stored in said instruction buffer for enabling a particular set of OPERATION decoder circuits identified thereby; a plurality of data registers having input lines and output lines; a plurality of normally disabled gating circuit groups, each such group being coupled to and controlled by a different OPERATION decoder circuit; each gating circuit group comprised of a plurality of gating circuits each having input and output lines; means connecting the gating circuit output lines of each gating circuit group in common and to the input lines of one of said data registers; means connecting the input lines of each gating circuit within a group to different data register output lines; timing means for providing spaced clock pulses defining successive processor cycles; and means responsive to said timing means for causing said OPERATION decoder circuits to simultaneously enable selected gating circuits identified by said stored OP CODE and OPERATION fields during each processor cycle.
 2. The data processing system of claim 1 including a data pad memory comprised of a plurality of locations, each capable of storing a multibit data word; pad address register means for uniquely identifying one of said data pad locations to selectively either produce a representation of the data word stored therein on output lines of said data pad or store a representation therein of a data word represented on input lines of said data pad; means connecting said data pad output lines to the input lines of certain ones of said gating circuits; and means connecting the output lines of at least one of said gating circuit groups to said data pad input lines.
 3. The data processing system of claim 2 wherein said pad address means comprises one of said data registers.
 4. The data processing system of claim 2 including a third memory comprised of a number of information storage locations significantly greater than the number of locations in said instruction memory; third memory address register means for uniquely identifying one of said third memory locations to selectively either produce a representation of the information stored therein on output lines of said third memory or store a representation therein of information represented on input lines of said third memory; and means connecting said third memory output lines to the input lines of certain ones of said gating circuits.
 5. A data processing system including: an instruction memory having a plurality of storage locations each capable of storing an instruction word comprised of a multibit OP CODE field and a plurality of multibit Operation fields; instruction storage means comprised of a number of bit stages; instruction address means for storing address information uniquely identifying one of said storage locations for entering at least a portion of the instRuction word stored therein into said instruction storage means; a plurality of multibit data registers each having bit output lines and bit input lines; a plurality of selectable sets of operation decoder circuits; an OP CODE decoding means responsive to the bit content of particular stages of said instruction storage means storing said OP CODE field for selecting a particular operation decoder circuit set identified thereby; a plurality of normally open gating circuits arranged in groups, each group being coupled to one of said operation decoder circuits, each gating circuit having bit output lines and bit input lines with the gating circuit bit output lines of the same group being connected in common to the bit input lines of one of said data registers; said gating circuit bit input lines of the same group being connected to bit output lines of different data registers; each of said operation decoder circuits within said selected decoder circuit set being responsive to the bit content of particular stages of said instruction storage means storing one of said Operation fields for enabling a gating circuit of the group associated therewith and identified by the bit content of said Operation field.
 6. The data processing system of claim 5 including arithmetic circuit means having bit output lines and first and second sets of bit input lines; and wherein said plurality of gating circuits includes at least one group of gating circuits each coupling the bit output lines of one of said data registers to a set of bit input lines of said arithmetic circuit means whereby both arithmetic and transfer operations can be executed in parallel in response to different operation fields of an instruction word.
 7. The data processing system of claim 5 including a data pad memory having a plurality of storage locations each capable of storing a data word, said data pad including data input and data output lines; pad address means for storing address information uniquely identifying one of said pad storage locations; and means responsive to said instruction word stored in said instruction storage means for accessing said identified data pad storage location to produce the data word stored therein on said data output lines or to write therein a data word applied to said data input lines.
 8. The data processing system of claim 7 wherein said plurality of gating circuits includes gating circuits having bit input lines coupled to said data pad output lines and gating circuits having bit output lines coupled to said data pad input lines.
 9. The data processing system of claim 7 wherein said instruction memory and said data memory are relatively small, fast access memories; and including a large external memory having a plurality of locations and including memory input and output lines; and wherein said plurality of gating circuits includes gating circuits having bit input lines coupled to said large memory output lines.
 10. The data processing system of claim 9 wherein said large memory includes address means for uniquely identifiying one of said large memory locations; means coupling the bit output lines of one of said data registers to said large memory input lines; and means responsive to said instruction word stored in said instruction means for accessing said identified large memory location to read data therefrom onto said output lines or to write data therein from said input lines. 